1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, the present invention relates to a semiconductor device having improved structural stability and enhanced performance, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
Semiconductor technology has been rapidly developed to manufacture highly integrated semiconductor devices that have greatly reduced sizes as dimensions of elements in the semiconductor devices have been continuously decreased. Many elements may be integrated in a unit cell of the semiconductor device, and also the semiconductor device may have improved response speed by reducing dimensions of the elements and time delay of a current passing among the elements. In addition, the semiconductor device may have low power consumption by reducing the current passing among the elements.
As the semiconductor device has a minute size, high integration degree and low power consumption, the semiconductor device may have improved performance. Since a transistor having a critical dimension of about 10 μm was developed in 1971, a recent transistor having a critical dimension of about 90 nm is introduced. In recent semiconductor technology, a semiconductor device has been reduced in size, and improved in response speed and integration degree when compared with a conventional semiconductor device. Further, a transistor that has a critical dimension of below about 65 nm is being studied.
However, short channel effect and leakage current may be generated in a semiconductor device including a transistor when the semiconductor device has a critical dimension of below about 90 nm. The short channel effect may be generated in accordance with length reduction of an effective channel of the transistor. The short channel effect is caused by diffusing N type impurities or P type impurities into a source region or a drain region of the transistor during thermal treatment of the transistor. When the effective channel of the transistor is reduced, an electrical short may be generated between the source region and the drain region of the transistor. To solve the above problems, there is provided a transistor having gates formed on three faces of a channel thereof. This transistor is generally referred to as a triple gate transistor. A conventional triple gate transistor is disclosed at Korean Patent No. 308,652 and Korean Patent Laid Open Publication No. 2001-8524.
FIG. 1A is a plan view illustrating a conventional triple gate transistor, and FIG. 1B is a perspective view illustrating the portion of the conventional triple gate transistor labeled “I” in FIG. 1A.
Referring to FIGS. 1A and 1B, the conventional triple gate transistor includes a semiconductor substrate 11, a buried insulation layer 13, a three-dimensional active region 16, and a gate structure 30. The gate structure 30 is formed on the buried insulation layer 13 to enclose the three-dimensional active region 16. That is, channel regions of the triple gate transistor are formed at portions where the gate structure 30 contacts the three-dimensional active region 16. The triple gate transistor may have improved electrical conductivity and prevent the short channel effect so that the triple gate transistor may have a critical dimension of below about 65 nm.
However, when a silicide layer is formed on source/drain regions of the triple gate transistor so as to improve electrical characteristics of the source/drain regions, the silicide layer may be formed on an entire active region as well as on the source/drain regions, thereby reducing the electrical characteristics of the triple gate transistor.
FIGS. 2A to 2C are cross-sectional views illustrating a method of manufacturing the conventional triple gate transistor taken along a line of II–II′ in FIG. 1A.
Referring to FIG. 2A, the triple gate transistor includes a semiconductor substrate 11, a buried insulation layer 13, an active region 16 and a gate structure 30. The gate structure 30 includes a gate insulation layer 32, a gate electrode 34, and a gate silicide layer 37.
An offset spacer 41 and a gate sidewall spacer 43 are sequentially formed on a sidewall of the gate structure 30. Source/drain regions 53 are formed in the active region 16, and source/drain extension regions 51 are formed adjacent to the source/drain regions 53. A source/drain offset spacer 61 and a source/drain sidewall spacer 63 are successively formed on a sidewall of the source/drain regions 53.
When a silicide layer 57 is formed on the source/drain regions 53 by siliciding a metal layer after the metal layer is formed on the source/drain regions 53, the silicide layer 57 is positioned on the source/drain regions 53 only because the sidewall of the source/drain regions 53 is covered with the source/drain offset and sidewall spacers 61 and 63.
As shown in FIG. 2B, however, a damaged portion III of the source/drain offset and sidewall spacers 61 and 63 may be generated in processes of manufacturing the triple gate transistor. The source/drain offset and sidewall spacers 61 and 63 including the damaged portion III may not completely protect the sidewall of the source/drain regions 53. Thus, the source/drain regions 53 are partially exposed through the damaged portion III of the source/drain offset and sidewall spacers 61 and 63. As a result, the silicide layer 57 may be formed on the sidewall of the source/drain regions 53 as well as on a surface portion of the source/drain regions 53. That is, a silicidation process of forming the silicide layer 57 may be advanced in directions IV and V relative to the surface and the sidewall of the source/drain regions 53.
Referring to FIG. 2C, a void 91 may be generated in the active region 16 to cause a failure of the triple gate transistor. In addition, silicidation intrusion 93 may be introduced in the source/drain regions 53 to cause damage to a source/drain junction and leakage current from the source/drain regions 53. Therefore, the triple gate transistor including the silicide layer 57 may not be formed when the silicide layer 57 is formed on the source/drain regions 53 using the damaged source/drain offset and sidewall spacers 61 and 63. This problem will be more fully explained with reference to FIGS. 3A and 3B.
FIGS. 3A and 3B are cross-sectional views illustrating a conventional silicidation process.
Referring to FIGS. 3A and 3B, a shrunk source/drain sidewall spacer 63 and a shrunk source/drain offset spacer 61 are sequentially formed on a sidewall of the source/drain regions 53. The sidewalls of the source/drain regions 53 are partially exposed due to the shrunk source/drain sidewall and offset spacers 63 and 61. After a metal layer 58 is formed on the source/drain regions 53 and on the exposed portion of the sidewall of the source/drain regions 53, a silicidation process is performed concerning the source/drain regions 53. As shown in FIGS. 3A and 3B, source/drain regions 53 of a relatively small transistor is entirely converted into a silicide layer 59, whereas most of source/drain regions 53 of a relatively large transistor is converted into a silicide layer 59 near a bottom portion thereof.
In the silicidation process, silicon in the source/drain regions 53 stoichiometrically reacts with metal in the metal layer 58 to thereby form the silicide layer 59. When the silicidation process may not stoichiometrically proceed between silicon and metal, the silicide layer 59 may be formed near channel regions of the triple gate transistor to achieve stoichiometric reaction between silicon and metal. This may result in generation of voids and intrusion of the triple gate transistor. Therefore, a spacer formed on a sidewall of source/drain regions of the triple gate transistor may completely protect the sidewall of the source/drain regions so as to prevent the triple gate transistor from being damaged.